With the advancement of wiring miniaturization for integrated circuits and the increase in wiring resistance and parasitic capacitance due to the wiring miniaturization, a signal propagation delay and its variation are increased, thereby making timing design furthermore difficult. Under such a background, a technique for improving timing is widely used in which a signal speed is increased by shortening the signal propagation delay of specific wirings using a thick-film wiring layer which has low wiring resistance and is formed above a wiring layer.
When this technique is applied, a thick-film wiring layer is required for signal wirings. In addition, it is preferable to lay out as many power-supply wirings as possible on the thick-film wiring layer so as to lower the impedance of a power-supply wiring network for the purpose of restricting voltage drop (IR drop) of a power-supply voltage due to the wiring resistance.
Notwithstanding, if separate thick-film wiring layers are prepared for signal wirings and power-supply wirings, respectively, an additional device structure is required, which results in higher fabrication cost and longer term for design changes. Therefore, as far as the voltage drop due to wiring resistance is within an allowable range, it is preferable to share the common thick-film wiring layer with both of signal wirings and power-supply wirings.
In a general design process for digital integrated circuits, power-supply wirings are laid out first and then ordinary signal wirings are laid out. Upon designing a digital integrated circuit in accordance with this order of steps, if power-supply wirings are laid out on the entire surface of a thick-film wiring layer first, signal wirings cannot be laid out on the wiring layer. If a portion of the thick-film wiring layer is preliminarily reserved as a space for signal wirings, the impedance of a power-supply wiring network increases compared to when no such space is provided and a power-supply voltage drops significantly due to wiring resistance, which cause malfunction of a semiconductor integrated circuit.
Different from the technique described above, there is also proposed a technique in which a voltage drop due to wiring resistance is restricted by conducting additional power-supply wirings after the signal wirings. However, even if this technique is applied without any technical artifice, it is impossible to restrict the voltage drop so much, but it takes much working load, because a space for conducting the additional power-supply wirings is limited.